1. Field of the Invention
The present invention relates generally to low power static memories, and more particularly pertains to a low power static memory array architecture that can significantly reduce the power required to drive a wordline, reduce bitline loading and provide sensing with less power. This memory architecture is very suitable for low power embedded cache memories and stand alone memories.
2. Discussion of the Prior Art
Static random access memories are commonly used for low power cache applications, such as in portable, handheld and pervasive devices and systems. Their power consumption can be reduced by limiting the number of circuits actively being used in the operation and retention of the data, with minimum leakage current in a nonactive mode. However due to demands for increased bandwidth and higher data rates, such as in mobile internet applications, higher power is consumed to maintain the additional activated memory cells and circuits in operation.
During a memory access (read or write operation), power consumption in the memory array is used primarily for turning on of the wordline, precharging of the bitline, and sensing of the data.
FIG. 1 illustrates a conventional SRAM memory design wherein the SRAM chip is divided into many subarrays. Each subarray is again divided into many (e.g. 256) addresses with each address being controlled by a single wordline WL of many (e.g. 256) wordlines. In a read or write data access operation, the data has to pass through a sense amplifier SA, and each sense amplifier SA is typically shared by several subarray columns, wherein each column is served by a pair of bitlines. For example, as shown in FIG. 1, one sense amplifier SA is shared by two columns 1 and 2, and is further shared by the top and bottom subarrays. In this arrangement, each sense amplifier SA serves 2 columns in each of 2 subarrays, with each column having 256 memory cells.
Although this arrangement is commonly used for SRAM designs to provide area savings in the SRAM chip, it is not practical for low power SRAM applications. Because in the common SRAM design, to save area, typically 2-4 times the number of sets of data cells are turned on by the same wordline while only one set of data from one set of data cells is needed.
The power consumption for a low power SRAM should be reduced as much as possible by eliminating any unnecessary power consumption. Only the necessary memory cells and sensing circuits should be turned on for data read and write operations.
Accordingly, it is a primary object of the present invention to provide a low power static memory array architecture that can significantly reduce the power required to drive a wordline, reduce bitline loading and provide sensing with less power. This memory architecture is very suitable for low power embedded cache memories and stand alone memories.
A further object of the subject invention is the provision of a low power static memory architecture with low power consumption that has the same internal data bus and a wide data bandwidth at the interface input/output to accommodate the demands of high bandwidth.